eZX Spectrum

A Spectrum-lineage home computer, designed from a clean sheet. One machine, three FPGA images: the full classic Spectrum range cycle-accurately, the ZX Spectrum Next, and a clean-slate redesign with a new CPU and chipset that imagines what a Spectrum could have become a few years after the last one shipped.

On the Next

The ZX Spectrum Next is the foundation any project in this space stands on. A small team extended the Spectrum line with deep care for the original — running the back catalogue faithfully, adding sprites and layered display and modern audio, and never breaking what came before. Compatibility came first and stayed first, and the result works.

The eZX takes the Next's compatibility work as a given and asks a different question.

Why this exists

If you started a Spectrum-lineage machine today, with no installed base to protect and no ULA timing to honour to the cycle, what would you build?

The answer turns out not to be "a faster Next." The answer is to have it all in one box — the classic Spectrum range exactly as the originals worked (every model timing-exact, including ULA contention and floating bus), the Next exactly as it is now (so every piece of Next software runs unchanged), and a separate design from scratch for the people who want to see where the line could go from here.

That's the eZX. The eZX primary is the default machine — the system boots into it. The Next-compatible image and the Classic Spectrum image are each one AntOS command away when you want them.

Three FPGA images, one machine

Classic Spectrum — cycle-accurate emulation of the pre-Next Spectrum range: 16K, 48K, +, 128, +2, +2A, +3, Pentagon 128, Timex TS2068 / TC2048, Didaktik, and Scorpion ZS-256 with Turbo+ mode. Bit-exact original ULA contention and floating-bus behaviour, the original per-model nominal Z80 clock, ULAplus for 64-colour mode where applicable, Timex high-resolution modes on the Timex entries, Pentagon 8×1 multicolour on the Pentagon entries. System RAM lives in BSRAM for single-cycle deterministic timing; ROM images live in HyperRAM. Interface 1, Interface 2 (with cartridge library in HyperRAM, instant cartridge swaps), DivIDE / DivMMC, Kempston, ZX Printer, and Microspeech are all available as togglable peripherals. The first hardware platform to combine ULAplus, Timex hires, and Pentagon multicolour selectable from one image. See Classic Spectrum image for the per-model details.

ZX Spectrum Next compatible — open source, derived from the upstream NextNano core for the display, audio, sprite, layer, paging, and peripheral subsystems. The CPU is the Z80NG, a clean-room Z80N-compatible CPU with prefetch buffer, μop cache, and an unlocked turbo mode that goes well beyond the Next's 28 MHz cap when running software that opts in. The instruction set, registers, opcodes, and cycle-accurate timing at the standard 28 MHz mode all match a real Next exactly — every Next instruction, display mode (including ULA+, ULANext, Layer 2, hi-res, hi-colour, tilemap, sprites, full 512-colour palette), and audio channel works as it does on real hardware. Anyone writing for the Next is writing for the eZX too. Plus a hardware debug subsystem the real Next can't match. See Next-compatible image for the upstream provenance and what's been added.

eZX primary — a clean-slate Spectrum-lineage chipset and a new CPU. None of the Next's compatibility constraints, because it isn't trying to be a Next. A new instruction set with Z80 ergonomics, a new chipset designed for the available silicon, a new way of thinking about Spectrum software for people who want to write something other than back-compatible Z80.

The three images are completely separate FPGA configurations stored in flash. The machine boots into the eZX primary; an AntOS command (spectrum-mode next or spectrum-mode classic 48k) reconfigures the FPGA with the chosen image when the user wants it, and spectrum-mode with no argument returns to eZX primary. Loading one replaces the other. They share the same physical hardware — FPGA, DDR3, HyperRAM, bridge chips, audio path, displays — and nothing else.

The eZX primary image implements the full composer-receiving interface — the same one the Ant64's FireStorm implements. DeMon and Pulse — the supervisor processors — maintain scene state in their own memory and stream per-frame display list descriptions (text cell grids, tilemap index maps, sprite display lists) to the eZX FPGA; the eZX primary composites all three description types as overlay layers on top of its native content. The physical link differs per supervisor — Pulse's descriptions ride its MIPI uplink, DeMon's ride two HDMI links to the FPGA (physically 2× LVDS sets of 4 channels each — the standard TMDS-pair physical layer HDMI uses) — but neither supervisor produces finished pixels, and the composer contract (descriptions in, chipset renders at scanout) is identical either way. Sprites, tiles, and text authored against the platform's shared 4bpp 16×16 texture format work unchanged on the eZX Spectrum and the Ant64. See the composer architecture for the full specification.

The Next-compatible and Classic Spectrum images implement a subset — just the text cell grid layer, enough for AntOS UI overlays (command line, status indicators, debug HUD). The reason is licensing: those two images are open source (NextNano upstream + Z80NG, see Open source where it makes sense below), and the full composer-receiving interface is closed-source IP that travels with the (non-open) eZX primary image. The text-cell receiver is small and simple enough to ship openly; the sprite display-list resolver, tilemap renderer, full 4bpp 16×16 texture pool, and genlock master function are all proprietary to the eZX primary chipset. Architecturally the subset is also a happy fit — the Next-compatible image's sprites and tilemaps belong to the NextNano core (so duplicating them on a composer path would be redundant), and the Classic Spectrum image is bit-exact ULA emulation with no native sprite engine to compose with anyway. AntOS UI overlays cleanly onto Spectrum, Spectrum Next, or eZX-primary visuals via the same DeMon-driven text-cell channel; only the eZX primary gets composer-driven sprites and tilemaps too.

Two memory configurations

The eZX ships in a base configuration with on-chip BSRAM and 16 MB of HyperRAM (Infineon S70KL1282), and offers a DDR3 SODIMM slot for a user-installable memory upgrade. The base configuration is a complete Spectrum-lineage machine — the entire Classic Spectrum image (every model, including Pentagon 1024) runs in the base configuration, and the Next-compatible image runs at every clock from cycle-accurate 28 MHz through unlocked turbo in the base configuration too, with the Z80NG's prefetch buffer absorbing HyperRAM's 70 ns effective first-byte latency (35 ns intrinsic, 2× from the dual-die fixed-latency mode). Video memory comfortably fits in the eZX's BSRAM tier as master copies (a strict improvement over the real Next, where video and system RAM share the same 2 MB pool).

What the DDR3 SODIMM upgrade adds: "expanded" eZX primary titles become available, and "compatibility-mode" titles — which already run fine on the base configuration — automatically get more asset room and faster code (composer texture fills, blitter, audio mixer, and the EE at 380 MHz collectively benefit from the bandwidth and capacity DDR3 provides). Standard 204-pin DDR3 SODIMMs work — 72-bit ECC DDR3-1600 SODIMMs in 1, 2, and 4 GB capacities (the supported sizes; 8 GB is theoretically possible at JEDEC's chip-density ceiling, and the eZX reserves 8 GB of address space, but only up to 4 GB is software-supported) run perfectly when clocked at the eZX's DDR3-800 (the GW5AST-LV138's maximum supported DDR3 data rate), with timing actually better than a native DDR3-800 part would deliver. The 8 extra bits per 72-bit word — the bits that would normally hold ECC syndromes — instead carry the eZX's per-byte debugger watch bits on data accesses and wide-mode extension nibbles on code fetches (extended register file, wider immediates, predication; see EE). One constraint to watch when buying: prefer single-rank (1R x8) modules to get full capacity — dual-rank (2R x8 / 18-chip) modules fit and work, but only the first rank is reachable (the FPGA controller IP drives one CS line), so half the labelled capacity is usable. See spec § Memory for the full detail and per-image memory architecture.

The product story is straightforward: a Spectrum-focused user buys the base unit and runs every Spectrum-lineage workload that's been documented since 1982 plus the full Next ecosystem at every speed including unlocked turbo — plus the eZX primary image itself, running "compatibility-mode" titles that share code, graphics, and sound across HyperRAM. Add a DDR3 SODIMM and compatibility-mode titles automatically get more asset room and faster code with no recompilation, while "expanded" eZX primary titles — the ones using genuine wide-mode CPU features — become available for the first time. Two configurations, one machine — and the base configuration is a complete Spectrum-and-Next machine, including eZX-primary software, in its own right.

Four joystick ports — far beyond any real Spectrum

The eZX inherits the Ant64's controller subsystem in full: four DE-9 joystick ports via the Sticky chipset, supporting Atari pads, Sega 3-button and 6-button pads, Genesis controllers, and analog paddle pairs. That's twice as many ports as the Spectrum +2/+3 ever offered, four times what the 48K supported via Kempston, and the same multiplayer-ready surface the Ant64 ships with.

For Classic Spectrum software the ports map to the standard Kempston / Sinclair / Cursor protocols at the I/O level — every joystick interface a Speccy game can ask for is available, with the eZX choosing which physical port answers which protocol at session start. For Next-compatible software the ports present as the Spectrum Next's standard joystick interfaces. For the eZX primary image the four ports are first-class multiplayer hardware — same controller story, same multiplayer arcade and party games as the Ant64. Modern USB controllers and Bluetooth gamepads also work through Pulse and are adapted into the same protocol surface that real software expects.

A Z80 heart in a new body

The eZX primary image runs a 64-bit RISC-V CPU — the same FireStorm Execution Engine (EE) the Ant64 runs. This sounds like an abandonment of Z80 tradition and isn't.

The base is RV64GC — flat 64-bit address space, three-address arithmetic, a real register file, the room to breathe that an 8-bit CPU never had. On top of that base, an extension called Xez adds the instructions a Z80 programmer reaches for instinctively: post-increment and post-decrement addressing, block moves and block compares, push/pop of multiple registers, decrement-and-branch, bit set/reset/test on memory operands, flag-setting arithmetic with the familiar Z/C/S/V/P conditional model. Xez is shared between the eZX and the Ant64, since both machines run the one EE.

You keep how you think about Spectrum software. You learn a handful of new mnemonics. See cpu for the eZX-specific integration and EE for the full CPU architecture.

Open source where it makes sense

The Next-compatible image is open source — the upstream NextNano core is open source and used as-is for the display, audio, sprite, layer, and paging subsystems, and the Z80NG CPU is a clean-room reimplementation copyrighted by Deluxe Pixel and released under a permissive open-source licence so any FPGA Spectrum-lineage project can adopt it. The Classic Spectrum image uses the same Z80NG CPU in Z80 strict mode, inheriting the same open-source status. The eZX primary image is not open source — its CPU, chipset, and composer-receiving RTL are closed; the specifications (CPU ISA including Xez and Xcrisp extensions, chipset programming model, display engine, assembler) are documented openly here. If anyone wants to study the design, port pieces of it, or absorb ideas into other projects, that's exactly what these docs are for; if they want the RTL itself, that stays inside the eZX primary image.

The composer-receiving interface is split along the same line: the text-cell receiver ships with the open-source images, the full sprite-and-tilemap composer RTL stays inside the closed eZX primary image (see Three FPGA images above).

Where to read next

• Hardware spec — what's in the box
• CPU — eZX overview, register file, CSRs, traps, reset
• Xcrisp extension and Xez extension — two of the custom RISC-V extensions shared with the Ant64's FireStorm EE
• Z80NG — the clean-room Z80N-compatible CPU used in the Next-compatible and Classic Spectrum images
• Nextgen — eZX improvements to the Spectrum Next compatibility image (BSRAM replication, 1080p output, ROM-tier HyperRAM, debug, turbo)
• Classic — eZX Classic Spectrum image (per-model emulation of 16K/48K/128/+2/+2A/+3/Pentagon/Timex/Didaktik/Scorpion with bit-exact ULA contention)
• eZX (chipset) — the eZX primary image's display, audio, and I/O
• HDMI output and RGB output — the two video paths
• Assembler — ezxasm syntax and toolchain
• Prototype — bring-up status and development workflow